FIG. 1 is a circuit diagram showing a conventional voltage comparator in which the operation is controlled by conventional switching control clock signals such as those shown in FIG. 2. In FIG. 1, a first terminal 1 to which a voltage V, is applied is coupled through a switch S1 to one terminal 3 of a coupling capacitor 10. A second terminal 2, to which a voltage V.sub.2 is applied, is coupled through a switch S2 also to the terminal 3 of the coupling capacitor 10. The other terminal 4 of the coupling capacitor 10 is connected to an input terminal 7 of a first inverting amplifier 11 which may comprise, for example, a CMOS device. Another switch S3 is connected between the input terminal 7 and an output terminal 5 of the inverting amplifier 11 so as to be in parallel with the inverting amplifier 11. The output terminal 5 of the first inverting amplifier 11 is connected to an input terminal 8 of a second inverting amplifier 12 which may comprise, for example, a CMOS device. An output terminal 9 of the second inverting amplifier 12 is connected to an output terminal 6 of the voltage comparator, at which an output voltage V.sub.3 is developed.
In the conventional voltage comparator shown in FIG. 1, the switches S1 and S3 are ON-OFF controlled by a switch controlling clock signal .phi. shown in FIG. 2, and the switch S2 is ON-OFF controlled by a switching controlling clock signal .phi. which is in opposite phase with the clock signal .phi.. In FIG. 2, the switch controlling clock signals .phi. and .phi. are produced from a basic clock signal .phi..sub.EXT. An interval T.sub.1 is a so-called "auto-zeroing" interval during which the input and output of the inverting amplifier 11 are coupled to each other to short-circuit the inverting amplifier 11 to thereby place the voltages at the input and output of the inverting amplifier 11 to a constant reference voltage which is discussed later. An interval T.sub.2 is a comparison interval during which the voltage V.sub.1 applied during the auto-zeroing interval and the voltage V.sub.2 applied during the interval T.sub.2 following the auto-zeroing interval T.sub.1 are compared with each other.
Next, the operation of the conventional voltage comparator of FIG. 1 is explained with reference to FIGS. 2 and 3. During an interval or auto-zeroing interval T.sub.1 during which the clock signal .phi. assumes a logic "1" value and the clock signal .phi. assumes a logic "0" value, the switches S1 and S3 are turned on as indicated by broken lines, while the switch S2 is turned off indicated also by a broken line. With the switch S1 turned on, the voltage V.sub.1 is applied to the terminal 3 of the coupling capacitor 10. With the switch S3 turned on, the input and output terminals 7 and 5 of the first CMOS inverting amplifier 11 are connected to each other, so that the voltages at the input and output terminals of the first CMOS inverting amplifier 11 assumes a constant voltage V.sub.0 which corresponds to the voltage at the intersection of a straight line L representing the relationship of "Input Voltage=Output Voltage" with a curve IN representing the transfer characteristic of the first CMOS inverting amplifier 11, shown in FIG. 3. As a result, a difference voltage V.sub.1 -V.sub.0 is applied across the coupling capacitor 10, so that charge Q.sub.1 expressed by the following equation (1) is stored on the coupling capacitor 10. EQU Q.sub.1 =C(V.sub.1 -V.sub.0) (1)
where C is a capacitance value of the capacitor 10.
During an interval when the clock signal .phi. is at the logic "0" and the clock signal .phi. is at the logic "1", i.e. during the comparison interval T.sub.2, the switches S1 and S3 are turned off as indicated by solid lines in FIG. 1, whereas the switch S2 is turned on as indicated by a solid line. With the switch S2 turned on, the voltage V.sub.2 is coupled to the terminal 3 of the coupling capacitor 10. Assuming that the application of the voltage V.sub.2 to the terminal 3 of the coupling capacitor 10 causes the input voltage to the first CMOS inverting amplifier 11 to change to V.sub.A, a difference voltage of V.sub.2 -V.sub.A is applied across the coupling capacitor 10, so that charge Q.sub.2 expressed by the following equation (2) is stored on the coupling capacitor 10. EQU Q.sub.2 =C(V.sub.2 -V.sub.A) (2)
During the comparison interval T.sub.2, the coupling capacitor 10 is neither charged nor discharged, and, therefore, the charge Q.sub.2 is equal to the charge Q.sub.1 which was stored during the auto-zeroing interval T.sub.1. Thus, the following relationship is established. EQU C(V.sub.1 -V.sub.0)=C(V.sub.2 -V.sub.A)
From this, the following equation (3) is derived. EQU V.sub.A -V.sub.0 =V.sub.2 -V.sub.1 ( 3)
The equation (3) indicates that a change in voltage from V.sub.1 to V.sub.2 at the terminal 3 of the coupling capacitor 10 causes the potential at the input terminal 7 of the first CMOS inverting amplifier 11 to change from V.sub.0 to V.sub.A. An offset V.sub.A -V.sub.0 produced due to the change of the input voltage to the CMOS inverting amplifier 11 from V.sub.0 to V.sub.A is amplified in accordance with the transfer characteristic IN of the CMOS inverting amplifier 11, and an output voltage V.sub.OUT is developed at the output terminal 5 in accordance with the result of the comparison of the voltages V.sub.1 and V.sub.2 applied to the terminal 3 of the coupling capacitor 10.
The output voltage V.sub.OUT is inverted and amplified by the second CMOS inverting amplifier 12 and is developed as an output voltage V.sub.3 at the output terminal 6 of the voltage comparator. To sum up, the voltage comparator shown in FIG. 1 operates to compare the input voltage V.sub.1 applied through the input terminal 1 and the switch S1 during the auto-zeroing interval T.sub.1 with the input voltage V.sub.2 applied through the input terminal 2 and the switch S2 during the comparison interval T.sub.2, and develops at its output terminal 6 a logic "1" or "0" depending on the relationship in magnitude between the input voltages V.sub.1 and V.sub.2.
In the conventional voltage comparator shown in FIG. 1, the width of each of the clock signals .phi. and .phi. for controlling the switches S1, S2, and S3 is proportional to the period of the basic clock signal .phi..sub.EXT which is supplied from an external circuit. Accordingly, as the frequency of the basic clock signal .phi..sub.EXT decreases, the duration of the auto-zeroing interval T.sub.1 becomes longer.
During the auto-zeroing interval T.sub.1, the switch S3 is turned on and, accordingly, the input and output voltages to and from the CMOS inverting amplifier 11 are equal to each other and equal to V.sub.0. When the input voltage to the first CMOS inverting amplifier 11 is between the threshold voltage V.sub.THP of a P-channel MOS (hereinafter referred to as PMOS) transistor and the threshold voltage V.sub.THN of an N-channel MOS (hereinafter referred to as NMOS) transistor of the inverting amplifier 11, and, therefore, the inverting amplifier 11 operates within a range indicated by hatching, as shown in FIG. 4, the PMOS and NMOS transistors of the inverting amplifier 11 are concurrently conductive. In particular, when the input voltage is in the vicinity of the voltage V.sub.0, both transistors operate in their saturation regions R.sub.SN and R.sub.SP, which causes large power to be consumed. In FIG. 4, R.sub.SN represents the saturation region of the NMOS transistor, and R.sub.UN represents the unsaturation region of the NMOS transistor. R.sub.SP and R.sub.UP represent the saturation and unsaturation regions of the PMOS transistor, respectively.
This voltage comparator has a disadvantage that as the auto-zeroing interval T.sub.1 increases, power consumption increases.
An object of the present invention is to provide a voltage comparator which is free of the above-stated disadvantage of the conventional voltage comparator, in which, regardless of the frequency of the basic clock signal, the duration of the auto-zeroing interval is maintained constant so that the power consumption of the voltage comparator can be minimized.